1. Field of the Invention
The present invention relates to a strucure of semi-custom LSI such as gate array devices and standard cell devices, and more particularly to an improvement of input/output cells in the semi-custom LSI.
2. Description of the Related Art
The gate-array chips or standard-cell chips have a plurality of I/O cells for input and output buffers and a plurality of basic cells used for a circuit construction. The I/O cells and basic cells are made of only circuit elements, to form semi-processed chips applicable to form many kinds of electronic circuits. The semi-processed chips are subjected to wiring process, in accordance with customer's request. Wirings are arbitrarily designed to achieve customer's requested function.
Elements in each I/O cells are wired to form an input or output buffer circuit. One bonding pad is added for respective I/O cells. Therefore, usage of one I/O cell is restricted to one buffer circuit for input or output. Furthermore, since bonding pads are arranged on peripheral portion of the chip to form one line on each side, the maximum number of bonding pads is limited by the used chip size, resulated in a limited number of input and output signals. The number of input and output signals may be increased by expanding chip size. This measurement is, however, retrogressive against the present trend of miniaturization and cost-reduction.